Digital Circuit Design(FPGA) - List of Manufacturers, Suppliers, Companies and Products | IPROS

[Data] Shirutoku Report No. 86 # Asynchronous Input Requires Measures

Caution is needed! It is important to properly address metastability measures during the design phase!

★★Shirutoku Report: Useful Information You Should Know★★ In digital circuits, there are synchronous circuits that are synchronized with a clock and asynchronous circuits that are not. The flip-flops (FF) used in synchronous circuits have timing specifications such as setup time (tSU) and hold time (tH) established as requirements for stable operation between the clock and input signals. This time, we will explain the handling of asynchronous input signals, which require caution in digital circuit design such as FPGA. [Contents] ■ Factors that cause logical circuits to malfunction ■ Measures to prevent impact on circuit operation ■ The number of flip-flops needs to be optimized ■ It is important to thoroughly implement metastability measures during the design phase *For more details, please refer to the PDF materials or feel free to contact us.*